As mentioned in a comment, there's a difference between a compiler barrier and a processor barrier. volatile and memory in the asm statement act as a compiler barrier, but the processor is still free to reorder instructions.

Processor barriers are special instructions that must be explicitly given, e.g. rdtscp, cpuid, memory fence instructions (mfence, lfence, ...) etc. lfence is also an execution barrier (on Intel, and more recently AMD), so it's interesting in combination with rdtsc (which isn't a memory operation, and is only ordered by *fen...